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lt8584 1 8584fb for more information www.linear.com/lt8584 typical application features description 2.5a monolithic active cell balancer with telemetry interface the lt ? 8584 is a monolithic flyback dc / dc converter de - signed to actively balance high voltage stacks of batteries . the high efficiency of a switching regulator significantly increases the achievable balancing current while reducing heat generation. active balancing also allows for capacity re - covery in stacks of mismatched batteries, a feat unattainable with passive balance systems. in a typical system, greater than 99% of the total battery capacity can be recovered . the lt8584 includes an integrated 6 a , 50 v power switch, reducing the design complexity of the application circuit. the part runs completely off of the cell which it is discharg - ing, removing the need for complicated biasing schemes commonly required for external power switches. the enable pin ( d in ) of the part is designed to work seamlessly with the ltc680x family of battery stack voltage monitoring ics. the lt8584 also provides system telemetry including current and temperature monitoring when used with the ltc680 x family of parts. when the lt8584 is disabled, less than 20 na of total quiescent current is typically consumed from the battery. l , lt , lt c , lt m , linear technology and the linear logo are registered trademarks and hot swap and isospi are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 6518733 and 6636021. applications n 2.5a typical average cell discharge current n integrated 6a, 50v power switch n integrates seamlessly with ltc680x family: no additional software required n selectable current and temperature monitors n ultralow quiescent current in shutdown n engineered for iso 26262 compliant systems n isolated balancing: n can return charge to top of stack n can return charge to any combination of cells in stack n can return charge to 12v battery for alternator replacement n can be paralleled for greater discharge capability n all quiescent current in operation taken from local cell n 16- lead tssop package n active battery stack balancing n electric and hybrid electric vehicles n fail-safe power supplies n energy storage systems lt8584 ltc6804 battery stack monitor measurable cellparameters 2.5a averagedischarge module + module + module C v + v C /c0 bat 12 + module C read cell parameters enable balancing ? ? lt8584 ta01a 2.5a averagedischarge module + bat 2 + module C ? ? 2.5a averagedischarge module + c12s12 lt8584 read cell parameters enable balancing c2s2 lt8584 read cell parameters enable balancing c1s1 bat 1 + module C ? ? extractable cellparameters ? r cable + r connector ? switching faults? undervoltage ? serial faults ? coulomb counting ? v cell ? i discharge ? v ref ? temperature 12-cell battery stack module with active balancing downloaded from: http:///
lt8584 2 8584fb for more information www.linear.com/lt8584 pin configuration absolute maximum ratings d in to gnd voltage ................................................. 10 v v in , v cell , v sns , mode , out , dchrg voltage ............................................ C0.3 v to 9v rtmr voltage .................................................... ( note 2) sw voltage ( note 3) .................................. C0.4 v to 50 v v in C v cell voltage ............................................ 200 mv v in C v sns voltage ............................................. 200 mv mode C v in voltage ............................................. 200 mv v sns , mode pin current ........................................ 1 ma v cell , out pin current ........................................ 10 ma sw pin negative current .......................................... C2a operating junction temperature range ( note 4) lt 8584 e ................................................. C40 c to 125 c lt 8584 i.................................................. C40 c to 125 c lt 8584 h ................................................ C40 c to 150 c storage temperature range .................. C65 c to 150 c lead temperature ( soldering , 10 sec ) ................... 300 c (note 1) fe package 16-lead plastic tssop 12 3 4 5 6 7 8 top view 1615 14 13 12 11 10 9 gndgnd gnd gnd modertmr d in out swsw sw sw dchrg v sns v cell v in 17 gnd t jmax = 150c, ja = 38c/w exposed pad (pin 17) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range lt8584efe#pbf lt8584efe#trpbf 8584fe 16-lead plastic tssop C40c to 125c lt8584ife#pbf lt8584ife#trpbf 8584fe 16-lead plastic tssop C40c to 125c lt8584hfe#pbf lt8584hfe#trpbf 8584fe 16-lead plastic tssop C40c to 150c consult lt c marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container . for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ downloaded from: http:///
lt8584 3 8584fb for more information www.linear.com/lt8584 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 4.2v, d in = gnd unless otherwise noted. (note 4) parameter conditions min typ max units v in recommended voltage range switching nonswitching l l 2.5 2.45 5.3 5.3 v v in quiescent current switching nonswitching in shutdown, d in = out in shutdown, d in = out l l 45 2.5 1 3 90 1 ma ma na a v in uvlo l 2.1 2.45 v switch dc current limit l 6 6.3 6.8 a current limit blanking time 450 ns switch v cesat i sw = 4a 200 mv switch leakage current v sw = 4.2v v sw = 4.2v l 5 70 4 na a switch maximum on t ime l 30 50 70 s switch short detection timeout note 5 l 0.5 0.85 1.2 s switch clamp voltage i sw = 2ma i sw = 6a 42 45 50 48 v v switch clamp blanking time note 6 80 200 360 ns dcm comparator trip voltage v sw C v vin l 40 95 150 mv dcm comparator propagation delay 200mv overdrive l 100 180 ns dcm blanking time 230 ns mode threshold 1.7 v d in shutdown threshold high low, referred to gnd l 1 1.2 1.4 v d in shutdown threshold hysteresis 100 mv d in data threshold high low, v th = v out C v din , mode = 0v l 0.3 0.7 0.9 v d in data threshold hysteresis v th = v out C v din , mode = 0v l 20 80 160 mv d in pin current v din = 0v v din = C1v l C6 C18 C3 C14 C1 C6 a a dchrg threshold mode t ied to v in l 0.5 0.8 1.1 v dchrg hysteresis mode tied to v in 100 mv dchrg pull-down current pin v oltage = 0.4v l 220 300 a dchrg pull-up current pin voltage = v in C 0.4v l 220 300 a rmtr pin high voltage r rtmr = 50k 1.22 v rmtr pin low voltage r rtmr = 50k 0 v v cell switch r dson 55 v sns dynamic input range gain error 8% l C30 70 mv v sns average input range gain error 3% l 15 45 mv v sns amplifier input referred offset v cell C v sns = 40mv l C1.1 1.1 mv v sns amplifier gain over v sns average input range l 18.7 19 19.3 v/v handshake voltage error measured with respect to: v mode1 = 0.2v v mode2 = 0.4v v mode3 = 0.6v v mode4 = 0.8v v sw,err = 1.2v v fault = 1.4v v fault = 1.4v l l l l l l C13 C14 C18 C22 C31 C35 C28 13 14 18 22 31 35 28 mv mv mv mv mv mv mv downloaded from: http:///
lt8584 4 8584fb for more information www.linear.com/lt8584 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime . note 2: do not apply a positive or negative voltage or current source to rtmr, otherwise permanent damage may occur. note 3: absmax rating refers to the maximum dc + ac leakage spike. do not exceed 40v dc on any of the sw pins. note 4: the lt8584e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization, and correlation with statistical process controls. the lt8584i is guaranteed over the full C40c to 125c operating junction temperature range. the lt8584h is guaranteed over the full C40c to 150c operating junction temperature range. note 5: this is a measure of time duration from the onset of the switch turning on to the time the short - circuit protection circuit is disabled. if the current comparator trips during this duration, the switch error latch is set . this indicates that the connection to the transformer primary is most likely shorted . note 6: this is a measure of time duration for the switch clamp to operate continuously without setting the switch error latch. if the switch clamp remains engaged longer than the switch clamp blanking time, the switch error latch is set and switching is disabled. note 7: the voltage proportional to temperature (v temp ) is measured on the out pin while in analog multiplexer mode 3 or 4. v temp must be subtracted from the v cell voltage that is measured while in analog mux mode 1. both measurements should be taken within 100ms of each other to reduce errors in absolute temperature calculation. symbol parameter conditions min typ max units t w decode window duration r rtmr = 10k r rtmr = 50k r rtmr = 100k r rtmr = 200k l l l l 1.76 8 15.6 29.3 1.86 8.4 16.4 31.5 1.96 8.8 17.2 33.7 ms ms ms ms decode window range l 1.76 33.7 ms t rst d in serial communication reset time l 10 s t 1 rtmr start-up time r rtmr = 10k l 1.8 5 s t 2 d in hold-off time l 50 s t 3 d in high time l 50 s t 4 d in low time l 50 s t 5 discharger activation time r rtmr = 10k 900 ns t 6 discharger deactivation time 2.1 s sr d in slew rate l 9 v/ms timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. mode = 0v. refer to timing diagram for parameter definition. (note 4) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 4.2v, d in = gnd unless otherwise noted. (note 4) electrical characteristics parameter conditions min typ max units handshake voltage line regulation from v vin = 2.5v to v vin = 4.2v 0.2 0.75 %/v v temp temperature coefficient (tc) note 7, k = (v cell C v temp )/tc 2 mv/k v temp v temp = v in C v out , t j = 25c 0.658 v out pin clamp voltage 10ma sourced from pin l 1.53 1.6 v out pin amplifier load regulation i out = 10a to 1ma l 0 0.2 0.4 %/ma downloaded from: http:///
lt8584 5 8584fb for more information www.linear.com/lt8584 typical performance characteristics v in internal uvlo switch current limit switch characteristics switch maximum on-time switch clamp voltage (i sw = 6a) dcm comparator threshold v in pin current switching disabled v in pin current total input leakage i vin + i vcell + i vsns + i sw t a = 25c, v in = v cell = v sns = 4.2v, unless otherwise noted. temperature (c) C60 current (ma) 2.62.5 2.4 2.3 2.2 2.1 2.0 20 8584 g01 140 100 C20 60 d in = 0v, part enabled pin voltage (v) 2 enabled current (ma) shdn current (ma) 54 3 2 1 0 0.80.6 0.4 0.2 0 6 8584 g02 4 8 temperature (c) C60 current (a) 54 3 2 1 0 20 8584 g03 140 100 C20 60 d in = out dchrg = 0vmode = v in temperature (c) C60 voltage (v) 2.62.5 2.4 2.3 2.2 2.1 2.0 20 8584 g04 140 100 C20 60 temperature (c) C60 current (a) 7.06.6 6.2 5.8 5.4 5.0 20 8584 g05 140 100 C20 60 temperature (c) C60 v ce,sat (v) beta (a/a) 0.60.5 0.4 0.3 0.2 4035 30 25 20 20 60 8584 g06 C20 140 100 i sw = 5.8a temperature (c) C60 time (s) 5048 46 44 42 40 20 8584 g07 140 100 C20 60 temperature (c) C60 voltage (v) 5553 51 49 47 45 20 8584 g08 140 100 C20 60 temperature (c) C60 voltage (mv) 130110 9070 50 20 8584 g09 140 100 C20 60 downloaded from: http:///
lt8584 6 8584fb for more information www.linear.com/lt8584 typical performance characteristics d in data threshold dchrg threshold (simple mode) dchrg drive current (serial mode) d in pin current d in pin current d in shdn threshold mode pin threshold v cell switch r ds(on) v temp t a = 25c, v in = v cell = v sns = 4.2v, unless otherwise noted. din voltage (v) C10 current (a) 180120 150 9060 30 0 C6 8584 g10 0 C2 C8 C4 4 2 temperature (c) C60 current (a) 0 C5 C10C15 20 8584 g11 140 100 C20 60 v din = 0v v din = C1v temperature (c) C60 voltage (v) 1.61.2 1.41.0 0.8 20 8584 g12 140 100 C20 60 rising falling temperature (c) C60 v out C v din (v) 1.00.6 0.80.4 0.2 0 20 8584 g13 140 100 C20 60 rising falling temperature (c) C60 voltage (v) 1.00.6 0.80.4 0.2 0 20 8584 g14 140 100 C20 60 rising falling temperature (c) C60 current (a) 400350 300 250 200 20 8584 g15 140 100 C20 60 sink source temperature (c) C60 voltage (v) 2.21.8 2.01.6 1.4 1.2 20 8584 g16 140 100 C20 60 temperature (c) C60 resistance () 120 80 100 6040 20 20 8584 g17 140 100 C20 60 v cell = 2.5v v cell = 3v v cell = 3.6v v cell = 4.2v temperature (c) C60 v cell C v out (v) 1.00.7 0.8 0.90.6 0.5 0.4 20 8584 g18 140 100 C20 60 downloaded from: http:///
lt8584 7 8584fb for more information www.linear.com/lt8584 typical performance characteristics t a = 25c, v in = v cell = v sns = 4.2v, unless otherwise noted. handshake voltage error decode window duration error out pin clamp voltage i out = 10ma out pin amplifier drive current out pin amplifier 1% settling time, c out = 220nf v sns transfer function v sns amplifier gain v sns amplifier input referred offset handshake voltage line regulation temperature (c) C60 gain (v/v) 19.5019.25 19.00 18.75 18.50 20 8584 g20 140 100 C20 60 temperature (c) C60 offset (v) 500250 0 C250C500 20 8584 g21 140 100 C20 60 temperature (c) C60 error voltage (mv) 10 50 C5 C10 20 8584 g22 140 100 C20 60 sw, err fault mode4 mode3 mode2 mode1 temperature (c) C60 regulation (%/v) 0.300.15 0.10 0.250.20 0.05 0 20 8584 g23 140 100 C20 60 temperature (c) C60 error (%) 32 1 0 C2 C1C3 20 8584 g24 140 100 C20 60 50k 10k 100k temperature (c) C60 v in C v out (v) 2.01.8 1.6 1.4 1.2 1.0 20 8584 g25 140 100 C20 60 temperature (c) C60 current (ma) 10 98 7 6 5 4 3 2 20 8584 g26 140 100 C20 60 sink source temperature (c) C60 time (s) 400300 200 100 0 20 8584 g27 140 100 C20 60 v in C v out = 1.4v 0.2v v in C v out = 0v 1.4v v cell C v sns (mv) 0 v cell C v out (mv) 1200 600 800 1000 400200 0 20 8584 g19 60 70 40 10 30 50 downloaded from: http:///
lt8584 8 8584fb for more information www.linear.com/lt8584 typical performance characteristics t a = 25c, v in = v cell = v sns = 4.2v, unless otherwise noted. average discharge current conversion efficiency switching waveform average discharge current conversion efficiency average discharge current conversion efficiency switching waveform switching waveform 2s/div t1 = na5920-ald1 = 2 series es1j v cell = 4.2v v stack = 400v v sw 10v/div i sw 2a/div 8584 g28 stack voltage (v stack + C v stack C) 50 discharge current (a) 2.62.2 2.42.0 1.8 1.6 1.4 1.2 1.0 150 8584 g29 300 250 400 350 100 200 v cell = 2.5v v cell = 3v v cell = 3.6v v cell = 4.2v t1 = na5920-ald1 = 2 series es1j stack voltage (v stack + C v stack C) 50 efficiency (%) 9080 8575 70 150 8584 g30 400 350 100 300 250 200 v cell = 2.5v v cell = 3v v cell = 3.6v v cell = 4.2v t1 = na5920-ald1 = 2 series es1j 2s/div t1 = na6252-ald1 = stps3h100u v cell = 4.2v v aux = 13.8v rcd snubber = 4.99k, 22nf v sw 10v/div i sw 2a/div 8584 g34 auxillary voltage (v) 10 discharge current (a) 3.02.4 2.6 2.82.2 2.0 8584 g35 35 25 30 20 15 v cell = 2.5v v cell = 3v v cell = 3.6v v cell = 4.2v t1 = na6252-ald1 = stps3h100u auxillary voltage (v) 6 efficiency (%) 9080 8575 70 8584 g36 36 24 30 18 12 v cell = 2.5v v cell = 3v v cell = 3.6v v cell = 4.2v t1 = na6252-ald1 = stps3h100u 2s/div t1 = na5743-ald1 = es1d v cell = 3.6v v module = 40v rcd snubber = 4.99k, 22nf v sw 10v/div i sw 2a/div 8584 g31 module voltage (v module + C v module C) 30 discharge current (a) 3.02.4 2.6 2.82.2 2.0 8584 g32 80 60 70 50 40 v cell = 2.5v v cell = 3v v cell = 3.6v v cell = 4.2v t1 = na5743-ald1 = es1d module voltage (v module + C v module C) 30 efficiency (%) 9080 8575 70 8584 g33 80 70 60 50 40 t1 = na5743-ald1 = es1d v cell = 2.5v v cell = 3v v cell = 3.6v v cell = 4.2v downloaded from: http:///
lt8584 9 8584fb for more information www.linear.com/lt8584 gnd ( pin1, pin 2, pin 3, pin 4, pin 17): must be soldered directly to local ground plane.mode ( pin 5): serial enable pin. connect this pin to ground to enable serial interface for analog mux control . connect this pin to v in to disable the analog mux. when the analog mux is disabled, the out pin defaults to v temp measurement. do not float this pin. rtmr ( pin 6): serial interface timer pin. place a resistor from this pin to ground to set the serial count duration window, t w . see the applications information section for proper resistor selection. d in ( pin 7): data input pin. take this pin to ground to initiate switching if mode pin is connected to v in , or to select the desired analog mux state if mode pin is tied to ground. this pin is designed to be directly driven from the ltc680x familys s pins. out ( pin 8): analog output pin. connect this pin to an accurate voltage monitor to measure a voltage propor - tional to the internal ic temperature, v temp , if mode pin is connected to v in , or measure the output of the internal analog mux if mode pin is connected to ground. in analog mux mode, the out pin allows voltage monitoring of the v cell pin, the v sns pin, or v temp . this pin is designed to be directly connected to the ltc680x familys c pins. must connect a compensation capacitor to this pin. see the applications information section for proper capacitor sizing and placement. v in ( pin 9): supply pin. connect this pin directly to the positive battery cell terminal. must be bypassed with high grade ( x5r or better) ceramic capacitor placed close to the transformers primary winding connection. v cell ( pin 10): cell voltage monitor pin. this pin provides a kelvin connection to the battery cell for accurate voltage monitoring. connect this pin directly to the positive battery cell terminal. the recommended cell voltage is 2.5 v to 5.3 v. v sns ( pin 11): voltage sense pin. connect this pin to the current sense resistor connected to the primary side of the transformer. use this pin to measure average current discharged from battery cell ( see the block diagram). mode pin must be connected to ground and the internal analog mux must have the v sns pin selected to use this feature . input current is determined as (v vcell C v vsns )/r sns . dchrg ( pin 12): discharge pin. the discharge pin can be configured as an input or output pin. connect mode pin to ground to configure dchrg as an output pin where dchrg is driven to v in during switching and driven to ground when switching is deactivated. the output configuration can be used to drive multiple lt8584s or other switching regulators in parallel, to boost discharge capability. connect mode pin high to configure dchrg as an input. when configured as an input pin, drive dchrg pin to v in to enable switching. note in this mode that se- rial communication is disabled and the d in pin must be grounded to initiate switching. sw ( pin 13, pin 14, pin 15, pin 16): switch pin. this is the collector of the internal 6 a npn power switch. minimize the metal trace area connected to this pin to minimize emi. connect the bottom side of the transformer primary to this pin. pin functions downloaded from: http:///
lt8584 10 8584fb for more information www.linear.com/lt8584 block diagram module+ + v module C moduleC t1 ? ? C + C + + C switch latch switch protection circuitry simplemode serialmode currentcomparator a2 a1 6.3m 40mv q1 q r s + ? dcm comparator 95mv v sw sw c tran 1v dchrg to parallel dischargers (optional) mode rtmr r rtmr ? + a3 1.22v v in v in timer 11-bit counter latchpower during timer chipenable to analog mux v sns amp 1.6v out pin clamp cellbeing balanced to c pinltc680x chip power control logic + ? + ? +? + ? v vin ? 0.2v v vin ? 0.4v v vin ? 0.6v v vin ? 0.8v v vin ? 1.2v v vin ? 1.4v v cell v temp v sns amp dietemperature to s pin (ltc680x) analog mux v in d in + ? m1 out gnd m2 5k v cell v in c vin v sns cell above cell below 8584 bd ? + 19x d1 c fbo r sns c vcell c out downloaded from: http:///
lt8584 11 8584fb for more information www.linear.com/lt8584 many systems use multiple battery cells connected in se- ries to increase the available capacity and voltage. in such systems, the individual battery cells must be constantly monitored to ensure that they operate within a controlled range. otherwise, the batterys capacity and life span may be compromised. linear technology offers the ltc680x family series of multicell battery stack monitors ( bsm) to accomplish this task. the ltc680x monitors each individual cell in the stack and communicates this information through a proprietary serial bus to a central processing unit. as a cell begins to reach the upper charge limit, commands are issued to the ltc680x to turn on that cells passive shunt, bypassing the charging current to that cell and allowing the current to continue to the rest of the cells. the passive shunt current and / or power capability constrains the maximum charging current for the battery stack. using a passive shunt is also inefficient, and the shunted current produces considerable heat at higher charging currents. the lt8584 solves the two limitations of passive shunting balancers by actively shunting the charging current and returning the energy back to the battery stack. instead of the energy being lost as heat, it is reused to charge the rest of the batteries in the stack. the architecture of the lt8584 also solves the problem of reduced run time when one or more of the cells in the stack reaches the lower safety voltage threshold before the entire stack capacity timing diagram operation is extracted. only active balancing can redistribute the charge from the stronger cells ( cells with higher voltage) to charge the weaker cells. this allows the weaker cells to continue to supply the load, extracting greater than 96% of entire stack capacity where passive balancing may only extract 80%. the lt8584 has an integrated 6 a switch designed to operate as a boundary mode flyback converter and provides 2.5 a average discharge current. the average discharge current is also scalable by using multiple lt8584s to balance each cell. note that each battery in the stack requires an lt8584 active cell balancer. the lt8584 flyback topology allows the charge to return between any two points in the battery stack. most applica - tions use a module approach and return the charge to a local set of 12 series-connected cells monitored by a 12 channel bsm ic, where the output of the flyback converter is designated as v module . the entire battery stack is then constructed using several 12- cell modules connected in series. a second approach is to return the charge to the entire battery stack, where the flyback output is desig - nated as v stack . a final option is to return the charge to an auxiliary power rail, designated as v aux . the lt8584 has two modes of operationselectable by the mode pinthat can be integrated with the ltc680x or other battery stack system. in simple mode, the lt8584 d in rtmr 8584 td dchrg t 2 t 3 t rst t 4 t 1 t 5 t 6 t w sr downloaded from: http:///
lt8584 12 8584fb for more information www.linear.com/lt8584 operation discharger is toggled on/off using a logic input pin. in serial mode, the lt8584 allows the user to measure the discharge current and the die temperature, in addition to the cell voltage. general flyback operation the first cycle will commence approximately 2 s after lt8584 has been commanded to discharge a cell. the lt8584 is configured as a flyback converter operating in boundary mode ( the edge of continuous operation), and has three basic states (see figure 1).1. primary-side charging when the switch latch is set, the internal npn switch turns on, forcing ( v vin C v cesat ) across the primary winding . consequently, current in the primary coil rises linearly at a rate of ( v vin C v cesat )/l pri . the input voltage is mir- rored on the secondary winding as C n ? ( v vin C v cesat ) which reverse-biases the secondary-side series diode and prevents current flow in the secondary winding. thus, energy is stored in the core of the transformer. 2. secondary-side energy transfer when current limit is reached, the current limit comparator resets the switch latch and the device enters the second phase of operation, secondary-side energy transfer. the energy stored in the transformer core forward-biases the series diode and current flows into the output capacitor and/or battery. during this time, the output voltage plus the diode drop is reflected back to the primary coil. 3. discontinuous mode detection during secondary - side energy transfer to the output capacitor , ( v module + v diode )/n will appear across the primary winding. a transformer with no energy cannot support a dc voltage, so the voltage across the primary winding will decay to zero. in other words, the collector of the internal npn, sw pins, will ring down from v vin + (v module + v diode )/n to v vin . when the sw pin voltage falls below v vin + 95 mv, the dcm comparator sets the switch latch and a new switch cycle begins. states 1-3 continue until the part is disabled. figure 1. simplified discharging waveforms 8584 f01 i pk i lpri i lsec v pri v sec v vin + t (1) primary-side charging (2) secondary-side energy transfer and output detection (3) discontinuous mode detection t t t t v sw v vin C v cesat l pri v vin C v cesat i pk n v module + v diode l sec C(v module + v diode ) n v module + v diode Cn(v vin C v cesat ) v module + v diode n v vin v cesat v cesat downloaded from: http:///
lt8584 13 8584fb for more information www.linear.com/lt8584 operation switch protection several protection features are included to reduce the likelihood of permanent damage to the internal power npn switch: the short - circuit detector, the high - impedance detector, the switch overvoltage protection ( ovp), and internal undervoltage lockout ( uvlo). these also alert the user when the integrity of the discharge converter has been compromised because of a fault. switching is disabled during fault conditions. short-circuit detector the short-circuit detector detects when the power npn switch turns off prematurely due to a short in the primary- side winding. if the current comparator trips before the 850ns short detection timeout, the switch error latch will trip. the out pin is driven to v vin C 1.2 v, v sw, err , during a switch error. the part must be reset to clear the switch error fault. high-impedance detector the high - impedance detector monitors how long the power npn switch has been on. if the switch remains on longer than 50 s , the switch maximum on - time, the switch error latch is set and the out pin is driven to v vin C 1.2 v , v sw , err . the part must be reset to clear the switch error fault . overvoltage protection (ovp) the ovp circuitry dynamically clamps the npn collectors sw pins to 50 v. this protects the internal power switch from entering breakdown and causing permanent dam - age. the clamp is also used as a primary-side snubber to absorb the leakage inductance energy. the 200 ns switch clamp blanking time determines if the clamp is absorbing a leakage spike or if the switch is turning off while the secondary of the transformer is open. if the switch clamp is on longer than approximately 200 ns, the switch error latch is set. the part must be reset to clear the switch error fault. internal undervoltage lockout (uvlo) lt8584 protects itself during a uvlo condition by disabling switching. the out pin is driven to v vin C 1.4 v, v fault , during a uvlo condition. a uvlo fault is non-latching and dominates over a switch fault ( serial mode requires v in to remain above 2 v for a uvlo fault to be non-latching ). once the uvlo condition is cleared, the out pin reverts to normal operation and switching resumes. if the switch fault latch was tripped prior to the uvlo event, the out pin will indicate a switch fault, v sw,err , only after the uvlo condition is cleared and switching would remain disabled . figure 2. simple mode configurations lt8584 local ic gnd local ic gnd local ic gnd local ic gnd stack+stackC v sns v cell gnd rtmr sw d in v in modedchrg out ? ? active low 8584 f02 on off lt8584 stack+stackC v sns v cell gnd rtmr sw d in v in modedchrg out ? ? active high on off downloaded from: http:///
lt8584 14 8584fb for more information www.linear.com/lt8584 operation simple mode operation connecting the mode pin to the v in pin configures the lt8584 as a simple discharger with a simple on/off shutdown pin. tw o shutdown options are provided to handle either an active high ( dchrg) or an active low input ( d in ), see figure 2. connect d in to ground and use dchrg pin for an active high input, or connect dchrg to v in and use d in as an active low input. the part will begin switching once the d in pin is low and dchrg is high. figure 3 shows the enable logic function. never drive d in more than 0.4 v below the local ground while operating in active-high simple mode. out pin in simple mode the out pin defaults to v temp , a voltage proportional to the die temperature, and is measured with respect to the cell voltage such that v temp = v vcell C v out . this can be used to monitor the internal die temperature for system diagnostics. the out pin will also output two distinct in - dication voltage levels, v vin C 1.4 v, v fault , for an internal uvlo condition, or v vin C 1.2 v, v sw, err , for a switch error. v temp is not allowed to exceed 1 v ( equivalent to 180c) 1 . this makes both the fault and switch error volt- ages deterministic. the switch error latch is set when the power npn switch has encountered a fault ( see the switch protection section for more details). figure 4. serial communication decode figure 3. simple mode enable logic 8584 f03 enable balancing dchrg din 8584 f04 shutdown shutdown serial decode enabled with correct state decode window 16.3ms r rtmr = 100k v cell selected v cell selected voltage mode handshake analog mux activated to desired input out will never be driven below v vin C 1.435v out pin clamp is active below v vin C 1.53v d in t t t rtmr 1.22v out v vin v vin v vin C 1.4v v vin C 0.2v v vin C 0.4v v vin C 0.6v v vin C 0.8v 1 not verified during production testing. downloaded from: http:///
lt8584 15 8584fb for more information www.linear.com/lt8584 operation serial mode operation use serial mode if monitoring the discharging current and/or the die temperature are required. connecting the mode pin to gnd enables serial communication. the d in pin is used to input serial data through a custom serial bus (see figures 4 and 5). serial mode safety features the lt8584 provides the user with several levels of safety and verification. the lt8584 has built in switch protec - tion that detects and halts power delivery during either a primary-side open or short, a secondary-side open or short, or an overvoltage on the primary or secondary. the lt8584 outputs the v sw,err handshake that can be read back by the battery stack monitor (bsm). the lt8584 also detects communication errors including too many or too few d in pulses or a uvlo condition. the lt8584 outputs the v fault handshake that can be read back by the bsm. the lt8584 also provides critical cell parameters including temperature, discharge current, cell voltage, and cell and connection dc resistance. these are all read back by the bsm. as the cell starts to age, the cell impedance increases . this allows the user to perform preventative maintenance, keeping the system down time to a minimum. finally, the lt8584 handshake voltages are 3% accurate independent references that can be used to verify that every channel in the bsm is measuring accurately. serial architecture power to the part is latched on the first negative edge of d in signal and remains latched for the duration of the decode window, t w . this allows the d in pin to be toggled for communicating serial data without resetting the part. the lt8584 counts the number of negative edges seen on the d in pin. note that the first edge, which initiates se- rial communication and latches the part, is not counted . there are four active modes the user can select as shown in table 1. handshaking is accomplished by reading the analog voltage on the out pin. handshaking voltages are asserted on the negative edge of the d in signal, cor- responding to the serial decode count.once the decode window expires and rtmr pin returns to ground, three actions are initiated: the out pin analog multiplexer switches to the desired measurement, the dis - charger turns on depending on selected mode in table 1, and the input power latch disables. note that the lt8584 can only be disabled after the decode window has expired and the d in pin has been taken high. table 1.serial mode states pulse count mode discharger st ate mux output handshake voltage (v vin C v out ) part disabled 0 disabled v cell n/a 0 fault disabled v fault 1.4 1 1 enabled v cell 0.2 2 2 enabled v sns 0.4 3 3 enabled v temp 0.6 4 4 disabled v temp 0.8 5 fault disabled v fault 1.4 figure 5. serial communication architecture 8584 f05 2-bit ripple counter y0y1 por rst qq sr mode 1mode 2 mode 3 mode 4 por qq sr 1-shot 11-bit ripple counter oscillator en por v dd por din y0 y11 rst v dd ab c d 2 4 decoder a b downloaded from: http:///
lt8584 16 8584fb for more information www.linear.com/lt8584 operation serial timer decode window the timer initiates on the first negative edge on the d in pin . rtmr pin remains high for the duration of the timer which signifies the decode window for the serial input counter . a resistor from the rtmr pin to ground sets the decode window duration. the duration can be accurately set from 1.9ms ( r rtmr = 10 k) to 31 ms ( r rtmr = 200 k). the timer can be set outside this range, but the accuracy decreases . the serial input counter stops counting and latches the data once the rtmr pin goes low; after which, the out pin amplifier input mux selects the desired measurement, and the discharger is set to the right state. serial communication fault modes the serial interface has several fault monitors that prevent entering undesired modes due to a communication error. the out pin is set to v vin C 1.4 v to indicate the lt8584 is in fault. the part remains in fault from the onset of rtmr going high until the first count is detected. if no count is seen by the serial input counter during the decode window , the fault is latched. if the serial input counter counts higher than 4 negative edges, the fault latch is set. a third latching fault occurs if an internal undervoltage lockout ( uvlo) is detected during the decode window . this protects against undesired operation if data latches or the serial input counter were reset. the part must be reset by taking d in high to clear a fault. d in pin and serial bus timing several internal passive filters are added to the data bus to prevent injected system noise corrupting serial com - munication. these filters have time constants that place constraints on the serial communication timing require- ments ( see the timing diagram). the lt8584 can reject up to 4 s of erroneous glitches on the d in pin in either direction. the power latch filter can also reject up to a 4s glitch on d in . the d in pin has built - in hysteresis of approximately 100 mv . this allows the serial input counter to recognize both slow and fast edges without erroneous behavior. the discharger activation or deactivation time is typically less than 3 s and is a direct indication of the switch enable latch state. out pin analog mux an internal multiplexer, mux, selects between v cell and the out pin amplifier based on one of the selected serial modes shown in table 1. the out pin amplifier has a 5k internal load and has several inputs including: v temp , the 19 ? v sns amplifier, and six handshake voltages. the internal mux defaults to v cell in shutdownconsuming no power in the processand provides a 55 ? nominal resistance from the v cell pin to the out pin. figure 6 shows the connection of the out pin to a bsm and its internal analog mux. the mux switches over to one of the handshake voltage levels once both the lt8584 and the decode window are activated. the out amplifier will indicate a fault at start-up until the serial input counter recognizes the first negative edge on d in . subsequent negative edges on d in cause the mux to select the handshake voltage corresponding to the number of edges counted. these voltage levels provide a means of verifying if the serial interface has recognized the correct count. note that the out pin amplifier has an approximate 200 s one percent settling time when driving a 220nf load capacitance. once the rtmr pin goes low, the mux selects the out pin mode corresponding to the number of serial input counts (see table 1 for available modes). the part can also be placed in shutdown when rtmr is low and the decode window has expired. v cell measurement the user can measure the cell voltage by measuring the voltage on the out pin either with the part disabled (discharger off) or with the part enabled in mode 1 ( dis - charger on), see table 1. the lt8584 uses an internal pmos switch with r dson = 55 to connect v cell to the out pin. note that any current flowing into or out of the out pin will cause a measurement error due to the ir drop across the switch. v sns 19 amplifier an amplifier is provided to allow the user to monitor the discharger current. this measurement can only be per - formed when the discharger is on ( mode 2). the differ- ential voltage between v vcell and v vsns is amplified 19. downloaded from: http:///
lt8584 17 8584fb for more information www.linear.com/lt8584 operation 8584 f06 lt8584 control vcell vsns r sns vin sw analog mux vcell vtemp vsns amp vin C 0.2vvin C 0.4v vin C 0.6v vin C 0.8v vin C 1.2v vin C 1.4v counter out c2 din gnd mode rtmr dchrg 1:4 ? ? +C v module lt8584 control vcell vsns r sns vin sw analog mux vcell vtemp vsns amp vin C 0.2vvin C 0.4v vin C 0.6v vin C 0.8v vin C 1.2v vin C 1.4v counter out din gnd mode rtmr dchrg 1:4 ? ? +C v module bat2 ++ bat1 s2 c1c0 s1 dcc1bit dcc2bit adc ltc680x figure 6. serial mode analog mux connection downloaded from: http:///
lt8584 18 8584fb for more information www.linear.com/lt8584 operation this reduces errors due to input offset in the measure- ment circuitry connected to the out pin. it also allows the use of low-value resistors, and thus, yields greater overall efficiency.for accuracy, the v in pin should be tied to the v sns pin to include both the lt8584 bias current and the internal npn base drive current. tying the v in pin to the v sns pin changes the overall gain to 20 x . tying the v in pin to the v cell measures transformer current only and the overall gain remains 19 x. the v sns amplifier has a C30 mv to 70 mv dynamic input range. internal filtering and circuit architecture allows ac - curate measurements even when the input current contains negative components. the v sns amplifier requires that the average input current remain positive. v vin C v out is not allowed to exceed 1 v during v sns measurement to guarantee that both v fault and v sw , err are deterministic. this sets the maximum average input range, v vcell C v vsns , to 50 mv . die temperature output the user can also monitor the die temperature by se - lecting either mode 3 ( discharger enabled) or mode 4 (discharger disabled). the voltage v vcell C v out , v temp , is proportional to the absolute temperature in degrees kelvin. thus, the user needs to take two measurements to calculate the die temperature. temperature data gives the user a second means to verify if the discharger is on as well as to monitor environmental conditions. v temp is not allowed to exceed 1 v ( equivalent to 180 c) 1 to make both v fault and v sw,err deterministic. the following equation is used to determine the internal die temperature in degrees celsius: t j ( c) = v temp ? 0.609 0.00197 where v temp = v vcell C v out and expressed in volts. although the absolute die temperature can deviate from the above equation by 25 c, the relationship between v temp and the change in die temperature is well defined. the offset error can be calibrated out using an accurate system temperature monitor like that in the ltc680 x family of parts. there is also a small v vcell dependence on v temp which can be corrected using the following expression: t j,corr (c) = t j,cal + (4.2v C v cell ) ? 2 c where t j,corr is the corrected die temperature and t j,cal is die temperature calculated from the previous equation. serial mode differential measurements all parameters including handshake voltages, v sns , and v temp are extracted differentially by taking two sequential measurements and doing a subtraction. figure 7 shows the method for extracting a given parameter, v par , from the highlighted lt8584. the lt8584 directly below the lt8584 under measurement must be forced to select v cell ( mode 0) and becomes the negative reference for both sequential measurements. table 2. mode selection during differential measurements serial mode state desired parameter 1st measurement 2nd measurement handshake voltage mode 0 during decode window v sns mode 1 mode 2 v temp , balancer enabled mode 1 mode 3 v temp , balancer disabled mode 0 mode 4 selecting v cell for the first measurement is performed by entering either mode 0 ( balancer disabled) or mode 1 (balancer enabled). use table 2 to determine which v cell to reference for a given parameter. all measurements are taken after the decode window has expired, unless otherwise noted. v par = 1 st measurement C (2nd measurement) = v cell C (v cell C v par ) the ltc6803 s channel above the channel under measure - ment will have a voltage higher than a standard cell, v cell + v par , see figure 7. the lt8584 was architected to protect the ltc6803 s adc inputs and to guarantee that they well never be stressed beyond their absolute maximum rating . dchrg output the dchrg pin allows the lt8584 to operate several dis - chargers in parallel. the dchrg pin goes high when the switch enable latch is set. the dchrg pin can be used to directly drive the dchrg pin of another lt8584 configured in simple mode ( mode pin connected to v in ) or to directly drive the shutdown pin of another power converter. it has the ability to sink or sour ce currents up to 300a. 1 not verified during production testing. downloaded from: http:///
lt8584 19 8584fb for more information www.linear.com/lt8584 operation figure 7. serial mode differential measurements 8584 f07 bat4 v cell4 +C lt8584 ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? out v cell gnd bat3 v cell3 +C lt8584 analog mux selecting v cell out v cell gnd bat2 v cell2 +C v cell4 +C v cell3 +C v cell2 +C lt8584 out v cell gnd bat1 lt8584 out v cell gnd analog mux selecting v cell adc ltc680x c3 c4c2 c1 c0 bat4 v cell4 +C lt8584 ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? out v cell gnd bat3 v cell3 +C lt8584 analog mux selecting parameter out v cell gnd bat2 v cell2 +C v cell4 + v par,3 v cell3 C v par,3 +C + C v cell2 +C lt8584 out v cell gnd bat1 lt8584 out v cell gnd analog mux selecting v cell adc ltc680x c3 c4c2 c1 c0 measurement 1 (v cell ) measurement 2 (v cell C v par ) downloaded from: http:///
lt8584 20 8584fb for more information www.linear.com/lt8584 applications information the lt8584 can be used as a discharger for balancing the charge in battery or supercapacitor stack systems. the user can choose either simple mode or serial mode. the lt8584 can be driven from any battery stack moni - tor such as the ltc680x. simple mode can be employed using either active high or active low logic, increasing its interface flexibility. component selection few external components are required to achieve balanc - ing. the only external components are the transformer, the output diode(s), the v in bypass capacitors, the r sns resistor ( for measuring discharge current), the r rtmr resis - tor ( for serial mode), and in some cases, a rcd snubber. the equations are shown for a module based approach described in the operation section. v module becomes v stack in all equations for applications returning charge to the entire stack voltage, and v module becomes vaux for all applications returning charge to an auxiliary power rail. transformer design the transformer design should yield overall converter efficiencies greater than 80%. this reduces heat dissipa - tion and allows for a smaller converter pcb footprint . a proper transformer design balances core losses with winding losses. the lt8584 converter operates in dcm where the flux swing in the transformer is the greatest . this shifts most of the heat loss from winding loss to core loss. reduce transformer core flux swing by lowering the air-gap permeability. a lower permeability requires more figure 8. effect of secondary winding capacitance turns to achieve a desired primary inductance; thus, a bal- ance can be achieved between core and winding losses . recommended transformers are given in table 3 that have been optimized for efficiency and size. use the following guidelines when designing new transformers. reduce the transformer size by designing the boundary- mode operating frequency between 100 khz and 150 khz. the peak primary current is fixed at 6 a by the chip. the transformer turns ratio, n, should be selected by optimiz - ing the converter input rms current, i.e. battery discharge current. the rms input current can be estimated as: i rms,in = i pk ? ? bm ? t on 3 note that negative switch current reduces the rms input current by effectively reducing the boundary-mode fre- quency , ? bm , ( see figure 8). reduce the overall reflected capacitance on the sw node by reducing the output diode and transformer interwinding parasitic capacitances. table 3. recommended transformers manufacturer part number recommended output range (v) rcd snubber required size w l h (mm) l pri (h) turns ratio (pri:sec) coilcraft www.coilcraft.com na6252-al na5743-al na5920-al* 10 to 35 30 to 80 100 to 400 yes ye s no 15.24 12.7 11.43 15.24 12.7 11.43 15.24 12.7 11.43 4 4 4 11:15 1:4 1:24 cooper bussmann www.cooperindustries.com ctx02-19175-r ctx02-19174-r ctx02-19176-r* 10 to 35 30 to 80 100 to 400 yes ye s no 15 13 12 15 13 12 15 13 12 4 4 4 3:4 1:4 1:24 wrth www.we-online.com 750314019_r01 750314018_r02 750314020_r01* 10 to 35 30 to 80 100 to 400 yes ye s no 15.24 13.34 11.43 15.24 13.34 11.43 15.24 13.34 11.43 4 4 4 3:4 1:4 1:24 * switch error latch may trip when starting at voltages lower than the recommended output range. 8584 f08 t v sw i sec i pri no sec. capacitance sec. discharge downloaded from: http:///
lt8584 21 8584fb for more information www.linear.com/lt8584 applications information figure 9. internal switch voltage waveform the rms input current can be increased by increasing the ratio between the effective switch on-time, t on , and off-time, t off . this off-time ratio is set by the transformer ratio, n. the following equation sets the switch off-time to approximately 1/3 of the switch on-time to optimize power transfer and efficiency. n = secondary turns primary turns = v module 3 ? v in the off-time ratio should not be decreased much beyond 1/5; otherwise, secondary-side energy transfer time be- comes too short, and the converter efficiency is reduced. some applications may require a lower rms current due to charging limitations or thermal dissipation limitations . both can be reduced by increasing the turns ratio, n. use the following equation to size the transformers primary inductance: l pri = 1 i pk ? ? bm ? 1 v in + n v module ?? ? ?? ? keep the primary inductance in the range of 2.2 h to 10h. the lower limit guarantees proper detection of an open circuit in the transformers secondary. the upper limit guarantees the high-impedance detector does not activate a false switch error during normal operation. leakage inductance leakage inductance causes added voltage stress on the internal power npn collector. the lt8584 uses an internal zener clamp to absorb this leakage spike energy and clamp the switch node voltage to 50 v. the leakage spike energy should be limited to improve efficiency. figure 9 shows the waveform of the internal npn switch. design the transformer to have minimum leakage induc - tance. keep both transformer windings tightly wound around the core air gap. using a bifilar winding or a sandwiched secondary decreases leakage inductance. note that increased interwinding capacitance is a trade-off with lower leakage inductance. several iterations may be required to optimize the transformer design. higher transformer turns ratios benefit from higher reflected capacitance that helps snub the leakage spike. n ratios less than 8 usually require an rcd snubber to help clamp this primary-side leakage spike and increase the converter efficiency. good values for the resistor and capacitor are 4.99k and 22nf , respectively. output diodethe output diode(s) are selected based on the maximum repetitive reverse voltage ( v rrm ) and the average forward current, i f( avg ) . the output diodes v rrm should at a mini- mum exceed v module + n ? v vin . the lt8584s internal ovp circuitry triggers at 50 v, and v rrm should therefore exceed n ?(50 + v vin ) to prevent damage to the output diode during an ovp event. note that the leakage spike will usually cause the ovp to trigger roughly 10% lower than the nominal reflected voltage on the primary. the output diodes i f( avg ) should exceed i pk /2n, the average short-circuit current. the average diode current is also a function of the output voltage. i f(avg) = i pk ? v vin 2 ? v module + n ? v vin ( ) the highest average diode current occurs at low output voltages and decreases as the output voltage increases. reverse recovery time, reverse bias leakage, and junc - tion capacitance should also be considered. all affect the overall charging efficiency. excessive diode reverse recovery times can cause appreciable discharging of the output stack, thereby decreasing charge recovery. choose a diode with a reverse recovery time of less than 75 ns. 8584 f06 t v sw 0v v vin + v stack /n must be less than 40v leakage spike clamped to 50v downloaded from: http:///
lt8584 22 8584fb for more information www.linear.com/lt8584 applications information diode leakage current under high reverse bias bleeds the output battery/capacitor stack of charge. choose a diode that has minimal reverse bias leakage current. diode junction capacitance is reflected back to the primary, and energy is lost during negative npn collection conduction. choose a diode with minimal junction capacitance. table 4 recommends several output diodes for various output voltages that have adequate reverse recovery times. flyback output capacitor every balancer flyback output must have a ceramic capaci - tor on its output. the output capacitor serves as a local, low impedance return path. it also aids during a connection failure, adding charge storage to allow the ovp circuit to detect an open. the capacitor should be sized to allow roughly 10 switch cycles when charging the output from ground to the nominal output voltage, v output,nom . use the following equation to size the output capacitor: c fbo 400 ? l primary v 2 output,nom the voltage surge rating must exceed 5 0? n. the volt- age surge rating is usually specified as a multiple of the maxi mum operating voltage. for capacitor maximum operating voltages less than 100 v, the surge rating is 2.5x. for operating voltage between 100 v and 630 v, the surge rating is typically 1.5 x; and for voltages higher than 1000v, the surge rating is 1.2x.bypass capacitors the lt8584 should be bypassed using 3 capacitors, c vin , c vcell , and c tran ( see block diagram), using a high - grade (x5r or better) ceramic capacitors. c vin should be placed close to the v in pin and should be sized between 1 f and 4.7f. c tran must be placed close to the transformers primary winding connection and the ic local ground. the capacitance should range between 47 f and 100 f. simple mode should have v sns , v cell , and d chrg shorted to v in , which provides an excellent landing for both the transformer primary and a single bypass cap ( see the recommended layout section). c vin may be omitted in simple mode provided that the c tran capacitor is in close proximity to the v in pin. c vcell is used for bulk capacitance and should be place close to the battery input connection. ceramic capacitors are a good choice for bypassing due to their moderate density, low internal series impedance, and very low leakage current. note that capacitor leak - age current at a given operating voltage goes down with increasing capacitor voltage rating. ceramic capacitors offer the lowest leakage current, while most electrolytic capacitors are quite leaky. table 4. recommended output diodes manufacturer recommended transformer turns ratio (n) range part number i f( avg ) (a) v rrm (v) t rr (ns) junction capacitance (pf) package stmicroelectronics 1 to 2 stps3h100u 3 100 n/a 90 smb stps2h100 ay * 2 100 n/a 50 sma 2 to 4 stth102 ay * 1 200 20 12 sma 10 to 24 stth112a 1 1200 75 sma fairchild semiconductor www.fairchildsemi.com 1 to 2 es2b 2 100 20 18 smb 2 to 4 es1d 1 200 15 7 sma 4 to 8 es1g 1 400 35 10 sma 6 to 12 es1j 1 600 35 8 sma vishay www.vishay.com 1 to 2 ss2h10* 2 100 n/a 70 smb u2b 2 100 20 16 smb 2 to 4 es1d 1 200 15 10 sma es07d-m* 1.2 200 25 5 smf 10 to 20 us1m 1 1000 50 10 sma *aec-q101 qualified downloaded from: http:///
lt8584 23 8584fb for more information www.linear.com/lt8584 applications information discharge current sense resistor the discharge current sense resistor, r sns , should only be used in serial mode. omit this resistor and short v sns and v cell to v in in simple mode. the maximum sense voltage between v vsns and v vcell is 50 mv. it is recom- mended to design for a nominal sense voltage of 30 mv. it is not recommended to design for a nominal sense voltage below 20 mv since the input offset voltage of the differential amplifier contributes more error at the lower range. r sns = v vcell ? v vsns i dis,av = 30mv 2.5a = 12m ? the internal amplifier amplifies the voltage difference between v vsns and v vcell 20 when v in is tied to v sns . the voltage is referenced from v cell such that: v vcell C v out = 20 ? ( r sns ? i dis, av ) the measurement is the average discharge current, i dis , av , and not the rms value. the output, v vin C v out , is clamped to a maximum of 1v.decode window resistor, r rtmr rtmr pin is used to set the duration of the decode window and is programmed by selecting the value of the resis - tor connected between rtmr and gnd. this pin is used in serial mode only. ground this pin when using simple mode. the decode window is programmable from 1.9 ms to 31 ms. set the decode window duration 30% longer than the required time to set the lt8584 in mode 4 and read back the handshake voltage. this allows the system to detect if there is a communication error. set r rtmr based on following equation: r rtmr (k ) = 0.015 ? t 2 w + 5.9 ? t w C 1.1 where r rtmr is given in k and t w is given in ms. the rtmr pin is driven to 1.22 v approximately 2 s after the part is first enabled. this indicates the decode window is active. the rtmr pin is taken low after the decode window expires. the internal decoder states are latched on the falling edge of rtmr ( see figure 4). the out pin multiplexer then selects the correct input corresponding to the programmed mode (refer to table 1). out pin compensation and filtering the out pin must have external compensation, c out , for all applications including both serial mode and simple mode. the external capacitor also provides necessary filtering for the input to the bsm. the out amplifier is internally compensated to handle capacitance ranging from 20nf to 220 nf. use 47 nf for most applications to yield approximately 100 s 1% settling time. a faster amplifier response can be achieved by adding a zero using a resis - tor in series with the external filter capacitor. use 4.7 nf capacitor with a 60 series resistor to achieve a sub-100 s settling time. note that in serial mode, the capacitors are placed between adjacent lt8584 out pins. this effectively doubles the compensation capacitance from the capacitor value used. the out amplifier also has internal filtering to both improve psrr and handle large-signal steps or spikes that may be present on the supply lines. additional filtering may be required in noisy environments . figure 10 shows a two-pole filter with the lt8584 operat- ing in serial mode. the resistors must be kept small to minimize error due to non-zero input currents into the bsm. the ltc6804 is guaranteed to have 2 a or less input bias current during measurement. there are two resistors in any given measurement path. thus, a 50 series resistor will introduce up to a 200 v error. d in pin current will also cause an error when enabling a particular lt8584, but the error term is canceled when making dif - ferential measurements. 8584 f10 out amp lt8584 out 50 c out 47nf 100nf out amp lt8584 out 50 c out 47nf 100nf to bsm 2a from bsm c out 47nf 100nf 2a figure 10. optional out pin filtering downloaded from: http:///
lt8584 24 8584fb for more information www.linear.com/lt8584 applications information hot swap? protection large currents are developed when hot swapping a bat- tery with a lt8584 application due to the large input bulk capacitance coupled with the low esr of the batteries. in most cases, the lt8584 should have no problem handling the overshoot voltage that follows the large inrush current. the downstream bsm, however, might encounter damage that requires additional steps and/or circuitry to protect against hot swapping. several solutions use a two-path method incorporating a pre-charge resistive path and a shunt path (see figure 11). this method has the disadvantage of lower efficiency and higher cost. use fets for m1 in figure 12 that have low r ds , on to maximize converter efficiency and have less than a 1.25 v v gs threshold. table 7 lists several recommended fets for m1. c1 should be sized such that c 1 c vin /500. the third active solution protects the flyback output capaci - tors. all flyback outputs sum together and flow through d13. during a hot swap condition, d13 will reverse bias and prevent a large inrush current into the flyback output capacitors. the peak repetitive reverse voltage, v rrm , should exceed the maximum module voltage, v module . several recommended diodes for d13 are given in table 8. mechanical solutiona mechanical approach may result in a more cost effective solution. a 10 resistor is used to pre-charge the c vin capacitor to the battery voltage, limiting the inrush cur- rent. after the c vin cap is charged, a mechanical short is connected across the resistor and remains there during all normal operations. there are three recommended solu - tions for the mechanical short : 1.) use a > 3 a rated jumper 2.) use a mechanical switch or 3.) use a staggered-pin battery connector. the staggered pin connection has the long pins connecting to lt8584 through the 10 resistor. the short pins connect directly to the lt8584, shorting out the 10 resistor. normal insertion has a delay on the order of milliseconds between the long pin connecting and short pin connecting to the circuit, allowing c vin to charge up through a current limiting resistor before the mechanical short is made. order of assembly the order of assembly of the battery stack, the lt8584 balancers, and the bsm can also mitigate hot swapping issues. having separate boards for both the lt8584 balancers and the bsm is recommended. this allows the lt8584 balancers to be built and connected during the battery stack assembly. the last step involves mating the battery stack and lt8584 assembly with the bsm board . additional filters on the inputs into the bsm also reduce possible issues during final assembly, see the out pin compensation and filtering section for more detail. 8584 f11 c vin v bat battery connection +C 10 lt8584 d in figure 11. dual path hot swap solution for most applications, use the recommended hot swap solution shown as active solution 1 in figure 12 and in the typical application section. several other mechanical, active, and order-of-assembly solutions are also given as alternatives or as supplements.active solution an active solution has the added advantage of automatic hot swap protection; no additional steps are needed when connecting batteries. tw o input protection solutions are shown with the first solution using only tvs diodes. d1 is selected to trigger around 6 v and to take the brunt of the connection input pulse. the reverse leakage current is more significant in low-voltage tvs s. table 5 gives several diodes for d1 that have adequate current and voltage characteristics while minimizing reverse leakage current. d2 provides secondary protection for the bsm inputs. these should be smaller than d 1 since the lt8584 s out pin limits current. table 6 gives several diodes that are optimal for d2. the second active solution has additional overvoltage protection via a fuse, f1, and a pre-charge mosfet circuit . downloaded from: http:///
lt8584 25 8584fb for more information www.linear.com/lt8584 applications information figure 12. active hot swap solutions 8584 f12 c vin d1 v bat battery connection +C lt8584 top of stack d2 to c12 c vin d1 v bat +C lt8584 d2 to c11 c vin d1 v bat +C lt8584 d2 to c10 active solution 1 flyback output hot swap protection c vin d1 v bat battery connection +C lt8584 10 top of stack c1 active solution 2 100k m1 c vin d1 v bat +C lt8584 10 f1, 5a f1, 5a c1 100k m1 c vin d1 v bat +C lt8584 10 f1, 5a bat12 + c1 100k m1 lt8584 d12a c12 t12 1:4 20k d13 module +module C gnd sw ? ? bat2 + lt8584 d2a c2 1f t2 1:4 gnd sw ? ? bat1 + lt8584 d1a c1 1f t1 1:4 gnd sw ? ? downloaded from: http:///
lt8584 26 8584fb for more information www.linear.com/lt8584 table 7. recommended fets for m1 in figure 12 manufacturer part number r ds,on (m) at v gs = 2.5v i ds,max (a) package fairchild semiconductor www.fairchildsemi.com fds4465 10.5 13.5 so-8 fds6576 20 11 so-8 fdma905p 21 10 microfet 2x2 fdma910pz 24 9.4 microfet 2x2 vishay www. vishay.com si7623dn 9 35 powerp ak 1212-8 si7615adn 9.8 35 powerpak 1212-8 sis407dn 13.8 25 powerpak 1212-8 sia447dj 19.4 12 powerpak sc-70 applications information table 5. recommended transient voltage suppressors ( tvs ) for d1 in figure 12 manufacturer part number reverse leakage (a) v p-p at i p-p package stmicroelectronics sm2t6v8a 50 at 5v 9.2v at 19.6a do-216aa sm4t6v7 ay * 20 at 5v 9.2v at 43.5a sma sma6t6v7 ay * 20 at 5v 9.1v at 68a sma vishay vesd05a1-02v 1 at 5v 12v at 16a sod-523 gsot05* 10 at 5v 12 at 30a sot-23 nxp pesd5v0s1ua 4 at 5v 13.5v at 25a sod-323 infineon esd5v0s1u-03w 20 at 5v 14v at 40a sod323 *aec-q101 qualified table 6. recommended transient voltage suppressors ( tvs ) for d2 in figure 12 manufacturer part number reverse leakage (a) v p-p at i p-p package stmicroelectronics esdalc6v1-1m2 0.1 at 3v 9.2v at 6a sod882 vishay vbus051bd-hd1 0.1 at 5v 16v at 3a llp1006-2l vesd05-02v 0.1 at 5v 20v at 6a sod-523 diode inc t5v0s5-7 0.05 at 5v 15v at 5a sod-523 nxp pesd9x5.0l* 0.2 at 5v 10v at 1a sod-882 *aec-q101 qualified table 8. recommended diodes for d13 in figure 12 manufacturer part number i f( avg ) (a) v rrm (v) package diodes, inc. www.diodes.com sbr8u60p5 8 60 powerdi5 pds760-13 7 60 powerdi5 vishay www.vishay.com v8p10-m3 8 100 to-277a ss10p6 7 60 to-277a downloaded from: http:///
lt8584 27 8584fb for more information www.linear.com/lt8584 operating paralleled lt8584s multiple lt8584s may be used if more discharge current is required. the lt8584 connected to a battery stack monitor ( ltc6804 is recommended) becomes the mas - ter balancer. connect its mode pin to ground. limit the maximum number of parallel slave balancers to 20. this gives a maximum discharge current of 50 a. other con- verters may also be used as a slave, including the lt3751 (must connect its v in to the cell above) and the lt3750. connect all slave mode pins to v in . this forces those parts into simple mode and makes their dchrg pin an input pin. applications information connect all slave dchrg pins ( shdn pins if using other converters) to the master dchrg pin. figure 13 shows a 5a discharger circuit using two lt8584s. each part operates asynchronously from the other one. use separate transformers for each lt8584 balancer. the slave balancers operate only when the master balancer is operating. a fault on the master balancer will turn off all slave balancers. a fault in any of the slave balancers will not turn off any of the other balancers. use an external sense resistor, r sns , and the v sns pin to determine if the average current is at the expected value. figure 13. lt8584 parallel operation lt8584 v in v sns r sns v cell gnd to adjacent out pin to adjacent out pin sw dchrg rtmr modeout d in slave balancer master balancer to c pinto s pin 8584 f13 module+moduleC ? ? lt8584 v in v sns v cell gnd sw dchrg rtmr modeout d in module+moduleC ? ? bat bat C bat C + bat C figure 14. lt 8584 suggested layout 12 3 4 5 6 7 8 thermal vias r1 1615 14 13 12 11 10 9 17 ? ? c fbo r sns v in dchrg d in out gnd gnd rtmr c vcell c vin c out v sns v cell v in batterystack ground top ofbattery stack batterystack ground top ofbattery stack d1 12 3 4 5 6 7 8 thermal vias serial mode simple mode 1615 14 13 12 11 10 9 17 ? ? c fbo t1 t1 v in d in out gnd gnd v in d1 8584 f14 c vtran cell input c vcell c vtran c out cell input downloaded from: http:///
lt8584 28 8584fb for more information www.linear.com/lt8584 applications information recommended layout the potentially high voltage operation of the lt8584 demands careful attention to the board layout, observing the following points: 1. minimize the board trace area of the high voltage end of the secondary winding. 2. keep the electrical path formed by c vtran , the primary of t1, the sw node, and ground as short as possible . increasing the length of this path effectively increases the leakage inductance of t1, resulting in excessive energy loss in the internal zener clamp or rcd snubber. 3. thermal vias should be added underneath the chips exposed pad, pin 17, to enhance the lt8584s thermal performance. these vias should go directly to a local ground plane with a minimum area of 650mm 2 . 4. make kelvin connections for v sns , v cell , and r sns to the battery cell when using the lt8584 in serial mode. the ir drop in the battery connection can be calibrated out using a software algorithm. consult application engineering. 5. care should be taken when routing v cell , v sns and v in connections. r trace in figure 15 should be minimized for better efficiency. r trace should never exceed 1 9? r sns . this guarantees that the out pin amplifier headroom is sufficient enough for reporting the v sns amplifier output . 6. minimize the total connection resistance from the battery terminals to the v cell and gnd pins of the lt8584. it is recommended to keep the total resistance less than 60m to improve converter efficiency. excessive ir drops in the pcb traces or connector terminals could also cause the lt8584 to prematurely enter uvlo. connecting to a battery stack monitor there are two methods used to connect the lt8584 bal - ancer to a battery stack monitor ( bsm): either a single - wire or two-wire. both have advantages and disadvantages. both methods may require kelvin connections for the bsm supply rails depending upon the magnitude of ir drop across the connections to the battery stack. in most cases, keeping the individual connection resistances less than 60 m allows the bsm supply rails to share the return path through rw 0 and rw 12, see figure 16. the single-wire connection is recommended due to com - plete system visibility of the wire connection impedance . the single-wire is also cheaper and more reliable due to fewer wire connections. see the typical application section for proper kelvin connection between adjacent lt8584 channels in single-wire mode. note that in the two-wire connection scheme, the ground connection impedance can not be determined when calculating wire impedance and will be invisible to the measurement system. on the flip side, the algorithms for computing two-wire connection impedance and back calculating v cell during discharging are more straightfor- ward. the two-wire method also has the advantage of only losing visibility of a single cell during an open connection instead of two as in the single-wire method. integrating with the ltc680x family the ltc680x family of parts are multi-cell battery stack monitors that are described in the operation section of this data sheet. for more information, consult the ltc680 x data sheets. several operational flavors are available with their inherent differences shown in table 9. table 9. ltc680x feature differences part communication compatible modes ltc6802-1 daisy chained serial simple mode only ltc6802-2 addressable parallel simple mode only ltc6804-1/ltc6803-1/ ltc6803-3 daisy chained serial serial / simple mode ltc6804-2/ltc6803-2/ltc6803-4 addressable parallel serial / simple mode 8584 f15 v bat +C r sns v cell v sns i sw r trace v in ? l pri q1 figure 15. r trace minimization downloaded from: http:///
lt8584 29 8584fb for more information www.linear.com/lt8584 figure 16. lt8584 battery connections 8584 f16 bat 12 r w12 r w11 v err v module + v module C + C lt8584 balancer on balancing current bat 11 r w10 v err + C balancing current bat 10 r w9 r w1 balancing current bat 1 r w0 lt8584 balancer on balancing current bat 12 r w12 lt8584 balancer on balancing current bat 11 r w11 lt8584 balancer on balancing current bat 10 r w10 lt8584 balancer on balancing current bat 1 r w1 lt8584 balancer on balancing current lt8584 balancer on lt8584 balancer on c11 c12 v + c10c1 c0 v C adc bsm two-wire battery connection single-wire battery connection c11 c12 v + c10c1 c0 v C adc bsm v module C v module + applications information the ltc6803 and ltc6804 draw only 3 a of static cur- rent on the s pin, allowing the lt8584 to be enabled without noticeable measurement error. the ltc6804 offers improved adc performance over the ltc6803 by reducing conversion time approximately 10 x and reduc - ing measurement error below 1.2 mv. the ltc6804 also utilizes isospi with improved rf-immunity.enable balancing in simple mode write a 1 to the corresponding dccx bit in the configura - tion register of the ltc680x. this pulls its s pin low and activates the lt8584. table 10 shows the required time to turn on one balancer where n = number of ltc680x in the system and ? = frequency of the scki clock. table 10. approximate time to enable one lt8584 step time (s) ltc6802-1/ltc6802-3 ltc6803-1/ltc6803-3 ltc6802-2/ltc6802-4 ltc6803-2/ltc6803-4 send wrcfg command, write 1 to enable balancer 16 + 56 ? n ( ) ? 72 ? note that the addressable serial interface is much faster when writing to a single channel in a multi-chip system. downloaded from: http:///
lt8584 30 8584fb for more information www.linear.com/lt8584 applications information enable balancing in serial mode in serial mode, the configuration register has to be writ- ten several times to toggle the dccx bit and pipe data into the serial bus. the rtmr resistor needs to be set accordingly to guarantee that enough time is allocated to enter any one of the four serial modes and read back the handshake voltage on the out pin. there are speed limitations when sending information to the lt8584 ( see the timing diagram). use table 11 to determine overall timing requirements. table 11. turning on lt8584 in mode 4 time (s) dccx state ltc6803-1/ ltc6803-2 ltc6803-2/ ltc6803-4 1 C d in low 16 + 56 ? n ( ) ? 72 ? 0 C d in high 1 C d in low (mode 1) 0 C d in high 1 C d in low (mode 2) 0 C d in high 1 C d in low (mode 3) 0 C d in high 1 C d in low (mode 4) total 16 + 56 ? n ( ) ? 9 ? 648 ? filtering and adc measurements the ltc680x has an internal multichannel differential adc that measures the voltage between each consecutive pair of c pins. figure 17 shows the adc connected to c(n) and c(n+1), measuring the difference between the two adjacent lt8584s out pins. most parameters require two measurements, one with the top lt8584 selecting v cell and another one with the top lt8584 selecting the desired parameter. the difference between these two measurements yields the desired parameter value. this is required since the ltc680x is not directly connected to the battery cells. see the serial mode differential measure - ments section for more detail.filter capacitors ( typically 47 nf) have to be placed between adjacent c pins to provide the required 16 khz lowpass filter for the adc input path. this provides 30 db of noise reduction. no external filter resistors are needed since the internal impedance from v cell to out is approximately 55. note that the effective capacitance on the out pin becomes 2 47nf or 94 nf. figure 17 has omitted these capacitors for the sake of simplicity ( see the typical ap - plications for proper connection of the filter capacitors). adequate bypass capacitors need to be connected from v in to ground for each lt8584 to provide a low-impedance path for high-frequency switching noise. ceramic capaci- tors work well for this purpose.several passive filters internal to the lt8584 are included to remove erroneous glitches on the d in pin that are up to 4s in duration.test circuit use the circuit in figure 18 for testing the lt8584 in serial mode without using a bsm. the inverter directly driving the lt8584 should be placed close to the lt8584 and have less than 1 v v gs thresholds. figure 19 shows typical serial communication waveforms using a 100 k timer resistor and a 2ms data period. lt8584 v in v cell mode gnd out d in 8584 f17 ltc6803/ltc6804 c(n+1)s(n+1) c(n) lt8584 v in v cell gnd out d in mode s(n) son c(nC1) son adc figure 17. lt c 6803/ lt c 6804 simplified connections downloaded from: http:///
lt8584 31 8584fb for more information www.linear.com/lt8584 applications information 8584 f18 lt8584 vishay si1035x vishay sfh6720t 2.3k 100 100 pulse generator 5vto 10v 100nf v cc gnd v out + C 10 g2g1 s2 d2 d1 s1 49.9 49.9 outgnd d in figure 18. serial mode test circuit figure 19. typical serial mode communication waveforms 2ms/div pulse counting previous mode selected mode4 handshake mode4 selected v rtmr 1v/div v din 2v/div v out 1v/div 8584 f19 reset downloaded from: http:///
lt8584 32 8584fb for more information www.linear.com/lt8584 typical applications stackable fast-charge 8 to 12-cell battery module, 4.6a discharge capability with 2 parallel lt 8584 per cell ? ? lt8584 slave v sns v in local v in local v in local v in sw t12b1:4 c12f1f module +C c12c1f module +C d12d v cell dchrgrtmr mode gnd out d in 8584 ta02a c12g47nf ? ? t12a1:4 d12b r12b100k lt8584 master r12a 5m r2a 5m r1a 5m v sns v in sw v cell dchrgrtmr mode gnd out d in c12a100f 2 c12e100f c12b22nf d12e r12c 4.99k battery stack to pcb connection d12a bat12 ? ? lt8584 slave v sns v in sw t2b1:4 c2f1f module +C c2c1f c2e100f c3d47nf d3c module +C d2d v cell dchrgrtmr mode gnd out d in c2g47nf ? ? t2a1:4 d2b r2b100k lt8584 master v sns v in sw v cell dchrgrtmr mode gnd out d in c2a100f 2 d2a ? ? lt8584 slave c2e100f v sns v in sw t1b1:4 c1f1f module +C c1c1f module +C d1d v cell dchrgrtmr mode gnd out d in c1g47nf ? ? t1a1:4 d1b r1b100k lt8584 master v sns v in sw v cell dchrgrtmr mode gnd out d in c1a100f 2 d1a c1347nf d13 c2d47nf d2c c1d47nf d1c ltc680x bsm v + v C c12s12 c2 s2 c1 c0 gpio1 m1 r pass 25010w module+moduleC + bat2 + bat1 + s1 kelvin connection to r1a c1a-c12a: 6.3v x5r or x7r ceramic capacitor c1b-c12b, c1h-c12h: 50v x5r or x7r ceramic capacitor c1c-c12c: 100v x5r or x7r ceramic capacitor c1d-c12d, c13: 50v npo ceramic capacitor c1e-c12e: 6.3v x5r or x7r ceramic capacitor c1f-c12f: 100v x5r or x7r ceramic capacitor c1g-c12g: 6.3v x5r or x7r ceramic capacitor d1a-d12a: stmicroelectronics sma6t6v7ay tvs diode d1b-d12b: fairchild es1d 200v, 1a ultrafast rectifier d1c-d12c, d13: stmicroelectronics esdalc6v1-1m2 tvs d1d-d12d: fairchild es1d 200v, 1a ultrafast rectifier d1e-d12e, d1f-d12f: fairchild ss16 60v, 1a m1: fairchild fdmc86102l 100v, 5.5a r1a-r12a: use 1% 1206 resistors r1b-r12b, r1c-r12c, r1d-r12d: use 1% 0603 resistors rpass: 10w wirewound t1a-t12a, t1b-t12b: coilcraft na5743-al u1: linear technology ltc680x family including but not limited to ltc6802, ltc6803, ltc6804 c12h22nf d12f r12d 4.99k c2b22nf d2e r2c 4.99k c2h22nf d2f r2d 4.99k c1b22nf d1e r1c 4.99k c1h22nf d1f r1d 4.99k average cell discharge current typical current measurement error module voltage (v module + C v module C) 30 discharge current (a) 6 54 3 35 8584 ta02b 50 45 40 v cell = 2.5v v cell = 3v v cell = 3.6v v cell = 4.2v module voltage (v module + C v module C) 30 error (%) 3 21 0 C2 C1C3 35 8584 ta02b 50 45 40 v cell = 2.5v v cell = 3v v cell = 3.6v v cell = 4.2v downloaded from: http:///
lt8584 33 8584fb for more information www.linear.com/lt8584 typical applications stackable fast-charge 8 to 12-cell battery module application notes 1. channels 3 through 11 are omitted for clarity. these channels should be integrated similar to channel 2. not all required components for the ltc680x are shown . consult the ltc680x data sheet for recommended components and their connections. 2. up to 20 lt8584 balancers may be connected in paral - lel to farther increase discharge current. the dchrg pin can also drive an enable pin of a separate dc/dc converter like the lt3750 capacitor charger. 3. multiple modules can be stacked in series to achieve a larger battery stack. each module must contain an integer multiple of the total number of cells in the stack . for instance, an 80 cell stack should be constructed with 8 modules each having 10 cells. use consecutive bsm channels starting with bsm channel 1 when populating a module with less than 12 channels. tie all unused ltc680x c pins to module+. 4. place one cne capacitor close to the master lt8584s transformer primary, and place the other cne capacitor close to the slave lt8584s transformer primary. the symbol n denotes a particular channel ranging from 1 to 12. 5. place rcd snubber composed of dnf, dne, rnc, rnd, cnb, cnh , as close as possible to the respective trans- former primary. the symbol n denotes a particular channel ranging from 1 to 12. 6. r pass and m1 may be omitted for applications using only one module in the stack. 7. each lt8584 channel should have no less than 650 mm 2 of pcb pad footprint for proper heat sinking. 8. consult application engineering for proper communica - tion with ltc680x family of parts as well as a proper algorithm for extracting cell parameters. 9. recommended for cells that operate within a 2.5 v to 5.3v range. stackable 8 to 12-cell battery module application notes see the last page typical application. 1. channels 4 through 11 are omitted for clarity. these channels should be integrated similar to channel 2. not all required components for the ltc680x are shown. consult the ltc680x data sheet for recommended components and their connections. 2. multiple modules can be stacked in series to achieve a larger battery stack. each module must contain an integer multiple of the total number of cells in the stack. for instance, an 80 cell stack should be constructed with 8 modules each having 10 cells. use consecutive bsm channels starting with bsm channel 1 when populating a module with less than 12 channels. tie all unused ltc680x c pins to module+. 3. place the cnb capacitor close to the lt8584s trans - former primary. the rcd snubber composed of cne, rnc and dnd should also be placed close the lt8584s transformer primary . the symbol n denotes a particular channel ranging from 1 to 12. 4. the bsm v + pin may share cell 12 s positive battery connection, and the bsm v C pin may share cell 0 s negative battery connection as long as the summa- tion of each battery connections pcb trace, wire, and inter connection resistance is less than 60m. 5. r pass and m1 may be omitted for applications using only one module in the stack. 6. each lt8584 channel should have no less than 650 mm 2 of pcb pad footprint for proper heat sinking. 7. consult application engineering for proper communica - tion with ltc680x family of parts as well as a proper algorithm for extracting cell parameters. 8. recommended for cells that operate within a 2.5 v to 5.3v range. downloaded from: http:///
lt8584 34 8584fb for more information www.linear.com/lt8584 fe16 (bc) tssop rev k 1013 0.09 C 0.20 (.0035 C .0079) 0 C 8 0.25 ref 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 1 3 4 5 6 7 8 10 detail b is the part of the lead frame feature for reference only no measurement purpose 9 4.90 C 5.10* (.193 C .201) 16 1514 13 12 11 1.10 (.0433) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 2.94 (.116) 0.48 (.019) ref 0.51 (.020) ref 0.195 C 0.30 (.0077 C .0118) typ 2 recommended solder pad layout 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 2.94 (.116) 3.58 (.141) 3.58 (.141) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note:1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 4. recommended minimum pcb metal size for exposed pad attachment see note 4 see note 5 5. bottom exposed paddle may have metal protrusion in this area. this region must be free of any exposed traces or vias on pcb layout 6.40 (.252) bsc fe package 16-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev k) exposed pad variation bc detail b 4.60 package description please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. downloaded from: http:///
lt8584 35 8584fb for more information www.linear.com/lt8584 revision history rev date description page number a 05/14 clarified features clarified electrical characteristicsclarified data threshold graph clarified out pin amplifier graph clarified operation description clarified operation description clarified applications information clarified figures 17, 18 13 6 7 1115 20, 24, 30 30, 31 b 8/14 clarified absolute maximum ratings clarified handshake voltage error conditions clarified d in pin function clarified block diagramclarified figure 1 clarified sense resistor formula clarified figure 16 in applications information 23 9 1012 23 29 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. downloaded from: http:///
lt8584 36 8584fb for more information www.linear.com/lt8584 c12c 1f module +C 8584 ta03a ? ? t12 1:4 c12b100f d12b c12e22nf r12c4.99k d12d r12b100k lt8584 r12a 12m r2a 12m v sns v in sw v cell dchrgrtmr mode gnd out d in c12a100f battery stack to pcb connection kelvin connection to r2a d12a bat12 c2c 1f c3d47nf d3c module +C ? ? t2 1:4 c2b100f d2b r2b100k lt8584 v sns v in sw v cell dchrgrtmr mode gnd out d in c2a100f d2a c1c 1f module +C ? ? t1 1:4 c1b100f d1b r1b100k lt8584 v sns v in sw v cell dchrgrtmr mode gnd out d in c1a100f d1a c1347nf d13 c2d47nf d2c c1d47nf d1c ltc6804 bsm v + v C c12s12 c2 s2 c1 s1 c0 gpio1 m1 r pass 5005w module+moduleC + bat2 + bat1 + r1a 12m kelvin connection to r1a c1a-c12a: 6.3v x5r or x7r ceramic capacitor c1b-c12b: 6.3v x5r or x7r ceramic capacitor c1c-c12c: 100v x5r or x7r ceramic capacitor c1d-c12d, c1e-c12e, c13: 50v npo ceramic capacitor d1a-d12a: stmicroelectronics sma6t6v7ay tvs diode d1b-d12b: fairchild es1d 200v ultrafast rectifier d1c-d12c, d13: stmicroelectronics esdalc6v1-1m2 tvs d1d-d12d: fairchild ss16 60v, 1a schottky m1: fairchild fdmc86102l 100v, 5.5a r1a-r12a: use 1% 1206 resistors r1b-r12b, r1c-r12c: use 1% 0603 resistors rpass: 2 parallel 2.5w wirewound t1-t12: coilcraft na5743-al u1: linear technology ltc680x family including but not limited to ltc6802, ltc6803, ltc6804 c2e22nf r2c4.99k d2d c1e22nf r1c4.99k d1d related parts typical application part number description comments ltc3300-1 high efficiency bidirectional multicell balancer synchronous flyback, up to 6 cells in series, 48-lead qfn ltc6803 multicell battery stack monitor measures up to 12 li-ion cells in series, ssop-44 ltc6804 multicell battery stack monitor measures up to 12 li-ion cells in series, built-in isospi?, ssop-48 stackable 8 to 12-cell battery module, lt 8584 in serial mode, single-wire configuration average cell discharge current module voltage (v module + C v module C) 30 discharge current (a) 3.0 2.42.2 2.82.6 2.0 35 8584 ta03b 50 45 40 v cell = 2.5v v cell = 3v v cell = 3.6v v cell = 4.2v module voltage (v module + C v module C) 30 output current (a) 0.300.10 0.05 0.20 0.250.15 0 35 8584 ta03c 50 45 40 v cell = 2.5v v cell = 3v v cell = 3.6v v cell = 4.2v average flyback output current ? linear technology corporation 2013 lt 0814 rev b ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/lt8584 downloaded from: http:///

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